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1 of 18 rev: 021406 general description the DS26521DK is an easy-to-use evaluation kit for the ds26521 t1/e1/j1 single-chip transceiver (sct). the DS26521DK is intended to be used as a stand- alone system. the board comes complete with a transceiver, transformer, termination resistors, configuration switches, network connectors, microprocessor, and rs-232 connector. the on- board processor and dallas chipview software give point-and-click access to configuration and status registers from a windows ? -based pc. on-board leds indicate receive loss-of-signal and interrupt status, as well as multiple clock and signal routing configurations. windows is a registered trademark of microsoft corp. design kit contents DS26521DK pc board cd_rom including: chipview software ds26521 definition files ds26521 initialization files DS26521DK data sheet ds26521 data sheet ds26521 errata sheet (if applicable) features demonstrates key functions of ds26521 t1/e1/j1 sct includes transceiver, transformers, and termination passives bnc connections for 75 ? e1 rj48 connector for 120 ? e1 and 100 ? t1 on-board processor and chipview software provide point-and-click access to the ds26521 register set accessible address/data bus with tri-state control to allow interface for external processor all equipment-side framer pins are easily accessible for external data source/sink leds for loss-of-signal and interrupt status easy-to-read silkscreen labels identify the signals associated with all connectors, jumpers, and leds ordering information part description DS26521DK design kit for ds26521 www.maxim-ic.com ds26521d k single t1/e1/j1 transceive r design kit downloaded from: http:///
DS26521DK 2 of 18 component list designation qty description supplier/part c01, cb07, cb08, cb10, cb12, cb16, cb18, cb19, cb21, cb23, cb26, cb32, cb39Ccb41 15 0.1 f 10%, 16v ceramic capacitors (0603) phycomp 06032r104k7b20d c02 1 1 f 10%, 16v ceramic capacitor (1206) panasonic ecj-3yb1c105k cb01, cb02, cb05, cb06, cb11, cb14, cb20, cb28, cb31, cb34, cb36, cb37 12 10 f 20%, 10v ceramic capacitors (1206) panasonic ecj-3yb1a106m cb03, cb04, cb13, cb17, cb24, cb25, cb29, cb38 8 4.7 f, 6.3v multilayer ceramic capacitors (0603) digi-key ecj-1vb0j475m cb09 1 560pf 5%, 50v ceramic capacitor (1206) digi-key 478-1489-2-nd cb15, cb22, cb27, cb33, cb35 5 0.1 f 20%, 16v x7r ceramic capacitors (0603) arrow 0603yc104mat2 cb30 1 470 f 20%, 6.3v tantalum capacitor (d case) digi-key 399-3002-1-nd db01 1 1a 40v schottky diode international rectifier 10bq040 ds01, ds02, ds05 3 red leds, smd panasonic ln1251c ds04 1 green led, smd panasonic ln1351c gnd_tp01C gnd_tp06 6 standard ground clips keystone 4954 h1Ch5, h10 6 kit, 4-40 hardware, 0.50 nylon standoff and nylon hex-nut lab stock 4-40kit4 j01Cj03, j06 4 10-pin, dual-row, vertical terminal strips samtec tsw-105-07-t-d j04, j08 2 5-pin right-angle bnc connectors trompetor ucbjr220 j05 1 db9 right-angle connector (long case) amp 747459-1 j07, j10 2 nonpopulated 14-pin, dual-row, vertical headers samtec nopop-hdr-tsw-107-14-t-d j09 1 100-mil, 2 x 7-position jumper lab stock j11 1 100-mil, 2-position jumper lab stock jb01 1 red banana plug socket, horizontal mouser electronics 164-6219 jb02 1 8-pin single-port rj48 connector molex 15-43-8588 jb03 1 black banana plug socket, horizontal mouser electronics 164-6218 jp01Cjp09, jp10 10 100-mil, 3- position jumpers lab stock r01Cr04, rb47 5 0 ? 5%, 1/8w resistors (1206) panasonic erj-8geyj0r00v r05, rb35Crb40, rb45, rb46 9 1.0k ? 5%, 1/16w resistors (0603) panasonic erj-3geyj102v downloaded from: http:///
DS26521DK 3 of 18 designation qty description supplier/part r06, r07, rb06, rb07, rb44, rb54, rb55 7 10k ? 5%, 1/16w resistors (0603) panasonic erj-3geyj103v rb01Crb05, rb11, rb23Crb26, rb28, rb29 12 30 ? 5%, 1/16w resistors (0603) panasonic erj-3geyj300v rb08, rb09, rb10, rb14Crb22, rb27, rb32, rb33, rb43, rb48 17 10k ? 5%, 1/16w resistors (0603) panasonic erj-3geyj103v rb12, rb13, rb50 3 330 ? 5%, 1/16w resistors (0603) panasonic erj-3geyj331v rb30, rb31 2 61.9 ? 1%, 1/10w resistors (0805) panasonic erj-6enf61r9v rb34 1 1.0m ? 5%, 1/16w resistor (0603) panasonic erj-3geyj105v rb41 1 51.1 ? 1%, 1/10w resistor (0805) panasonic erj-6enf51r1v rb42 1 10k ? 1%, 1/10w resistor (0805) panasonic erj-6enf1002v rb51 1 0 ? 5%, 1/16w resistor (0603) panasonic erj-3gey0r00v rb52 1 330 ? 5%, 1/16w resistor (0603) panasonic erj-3geyj331v rb53 1 1.0k ? 5%, 1/16w resistor (0603) panasonic erj-3geyj102v sw01 1 4-pin single-pole switch panasonic evqpae04m tb01 1 16-pin smt transformer pulse engineering tx1099 tp01, tp02 2 testpoints, one plated hole do not stuff lab stock u01, u02 2 cypress sram lab stock u03 1 single t1/e1/j1 transceiver, 64-pin, 10mm x 10mm lqfp dallas semiconductor ds26521 u04 1 mmc2107 processor motorola mmc2107 u05 1 1.2v fpga 144-pin, 20mm x 20mm tqfp lattice lfec3e-3t144c u06 1 3v to 5v regulating charge pump maxim max1686heua ub01 1 dual rs-232 transceivers with 3.3v/5v internal capacitors maxim na ub02 1 microprocessor voltage monitor, 2.93v reset, 4-pin sot143 maxim max811seus-t ub04 1 spi serial eeprom, 2m, 2.7v to 3.6v, 8-pin so atmel at25f2048n-10su-2.7 ub05 1 ldo regulator with reset, 1.20v output, 300ma, 6-pin sot23 maxim max1963ezt120-t yb01 1 oscillator, crystal clock 3.3v, 1.544mhz saronix nth039a3-1.5440 downloaded from: http:///
DS26521DK 4 of 18 designation qty description supplier/part yb02 1 oscillator, crystal clock 3.3v, 2.048mhz saronix nth039a3-2.0480 xb01 1 8.0mhz low-profile crystal pei sales inc. ec1-8.000m board floorplan pc board errata DS26521DK01a0 10/10/2005: there is no errata for the DS26521DK01a0 design. DS26521DK02a0 11/22/2005: there is no errata for the DS26521DK02a0 design. ds26521 fpga config prom lattice ec3 fpga fpg a jtag rlos led rlf led int led transformer 1.2v fpga supply rj48 bnc rx bnc tx testpoints: ds26521 address[12..0] data[7..0] int, cs, rw, rd testpoints: tser, rser, tssyncio, tsync, rsync, refclkio, mclk, rsig, tsig, testpoints: bpclk, mclk, rsysclk, tsysclk, tclk, rclk oscillator selection 1.544mhz, 2.048mhz ds26521 jtag 5v processor flash supply mmc2107 processor processor sram rs-232 db9 connector board power 3.3v banana plugs testpoints: spi_cpol, spi_cpha, spi_swap, spi_sel, bts, txenable testpoints: rchblk_clk, rlf_ltc, al_rsigf, rm_rfsync, tchblk_clk downloaded from: http:///
DS26521DK 5 of 18 basic operation this design kit relies upon several supporting files, wh ich are available for downloading on our website at www.maxim-ic.com/DS26521DK quickview page. hardware configuration ? supply 3.3v to the banana-plug rec eptacles marked gnd and vcc_3.3v. ? install the following jumpers (detailed in table 2): ? jp01connect mclk to 2.048mhz (for both t1 and e1). ? connect jp02 mclk to rsysclk, jp03 mc lk to tsysclk, jp04 tclk to rclk. ? jp08 spi_sel to gnd, jp09 bts to vcc, txenable to vcc. ? from the programs menu, launch the host application named chipview.exe . run the chipview application. if the default installation options were used, click t he start button on the windows toolbar and select programs chipview chipview . general: ? upon power-up, the rlf and al_los leds (red) will be lit, and the int led (red) will not be lit. the board will draw approximately 200ma at power-up. quick setup (register view) ? the pc will load chipview, offering a choice among demo mode, register view, and terminal mode. select register view. ? the program will request a definition file. navigate to the . def files in the t1 or e1 folder, then select the file named ds26521_global_t1.def (t1 mode) or ds26521_global_e1.def (e1 mode). note: through the links section this will also load t he liu def file and framer def file. ? the register view screen will appear, showing the regi ster names, acronyms, a nd values for the ds26521. ? predefined register settings for several functi ons are available as initialization files. ? .ini files are loaded by selecting the menu f ile r eg ini file l oad ini file. ? load the .ini file load_t1_lbo0_0_133_impmatchon.ini (t1 mode) or load_e1_75_impmatchon.ini (e1 mode). ? after loading the .ini file, the following may be observed: ? the ds26521 begins transmitting ais with impedance match. ? the al_los leds extinguishes upon external loopback. miscellaneous: ? the ds26521 uses three register definition files. all three files are loaded when the ds26521_global*.def file is loaded. individual files are selected from the d ef file selection menu in chipview. address map the on-board microcontroller is configured to start the user address space at 0x81000000. all offsets given below are relative to the beginning of the user address space. table 1. address map offset device description 0x0000 to 0x0087 fpga board identification and fpga test registers 0x1000 to 0x2fff ds26521 ds26521 framer, liu, and bert registers downloaded from: http:///
DS26521DK 6 of 18 testpoints a nd connectors the DS26521DK has several connectors, testpoints, oscill ators, and jumpers. table 2 provides a description of these signals, given in order of appearance on the pc boar d, from left to right then top to bottom (with the board held so that the rs-232 conne ctor is on the top edge). table 2. main board pc board configuration silkscreen reference function default setting schematic page description vcc 3.3v (banana plug) power supply vdd 3.3v 2 system vdd. always connected to power supply. gnd (banana plug) power supply ground gnd 2 system ground. always connected to power supply. j05 rs232 connector connected to host pc 8 used for communication with host pc. basic setting is 57.6k baud, 8 bits, no stop bit, 1 parity bit (57.6, 8, n, 1). j09 once bdm connector 8 once debug connector for mmc2107 processor sw01 system reset 6 system reset. connects to all device reset pins. j11 flash vpp jumper not installed 8 provides flash programming voltage (5v) to processor j01 fpga, jtag 11 jtag connector for lattice ec3 fpga tp01, tp02 fpga, testpoint 11 fpga init and done pins j03 ds26521 testpoints 5 testpoints for ds26521 pins: rchblk_clk, rlf_ltc, al_rsigf, rm_rfsync, tchblk_clk j06 ds26521 jtag - 3 jtag connector for ds26521 yb01, yb02 (bottom side of pc board) oscillators 5 oscillators for 2.048mhz and 1.544mhz j07, j10 testpoints 10 testpoints for ds26521 address/data bus and control lines j10.12 + j10.14 bus tri-state not jumpered 10 jp01 mclk selection jumpered pins 2+3 5 mclk selection: 1.544mhz, 2.048mhz (default) jp02 rsysclk selection jumpered pins 1+2 5 rsysclk selection: mclk (default), bpclk jp03 tsysclk selection jumpered pins 1+2 5 tsysclk selection: mclk (default), bpclk jp04 tclk selection jumpered pins 1.2 5 tclk selection: rclk (default), mclk j02 ds26521 testpoints 5 testpoints for ds26521 pins: tser, rser, tssyncio, tsync, rsync, refclkio, mclk, rsig, tsig jp05 spi_cpol bias not jumpered 3 spi_cpol selection: pulldown, pullup jp06 spi_cpha bias not jumpered 3 spi_cpha selection: pulldown, pullup jp07 spi_swap bias not jumpered 3 spi_s wap selection: pulldown, pullup jp08 spi_sel bias jumpered pins 1+2 3 spi_sel selection: pulldown (default), pullup jp09 bts bias jumpered pins 2+3 3 bts selection: pulldown, pullup (default) jp10 txenable bias jumpered pins 2+3 3 txenable selection: pulldown, pullup (default) j04, j08 network bnc 4 bnc for 75 ? network connection jb02 network rj48 4 rj48 network connection downloaded from: http:///
DS26521DK 7 of 18 maxim/dallas semiconductor cannot assume res ponsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxi m/dallas semiconductor reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2006 maxim integrated products ? printed usa the maxim logo is a registered trademark of maxim integrated products, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. ds26521 information for more information about the ds26521, consult the ds26521 data sheet available on our website at www.maxim-ic.com/ds26521 . software downloads are also available for this design kit. DS26521DK information for more information about the DS26521DK, including software downloads, consult the DS26521DK data sheet available on our website at www.maxim-ic.com/DS26521DK . technical support for additional technical support, please e-mail your questions to telecom.support@dalsemi.com . schematics the DS26521DK schematics are featured in the following pages. downloaded from: http:///
microprocessor hierarchy block pages 06-11 DS26521DK hierarchy block pages 03-05 only signals with import/outport connectors have connection outside the hierarchy block. these signals appear as pins on the hierarchy block connector notes: each hierarchy block is independent of the next. ds26521 design kit page 02: decoupling / mounting holes contents page 01: ds26521 design kit and engineering evaluation top level hierarchy blocks pages 06-11: microprocessorand interface pages 03-05: ds26521 device, line buildout and testpoints cr-1 : @\_ztop_lib\.\_ds26521topdn_\(sch_1):page1 DS26521DK top level DS26521DK02a0 10/26/2005 1/2(block) 1/11(total) steve scully block name: _ds26521topdn_. parent block: reset521 a_dut<12..0> d_dut<7..0> wr_dut cs_x1 int521 rd_dut page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 _motprocrescard_dn spi_miso spi_mosispi_sck spi_cs reset cs_x1 cs_x2 int2int3 int5 d_dut<7..0> wr_dut rd_dut cs_x5 cs_x4 cs_x3 int4 a_dut_<12..0> _DS26521DK01a0dutdn_ cs_x1 int521 reset521 a_dut<12..0> d_dut<7..0> wr_dut rd_dut downloaded from: http:///
cr-2 : @\_ztop_lib\.\_ds26521topdn_\(sch_1):page2 steve scully 10/26/2005 2/2(block) block name: _ds26521topdn_. parent block: DS26521DK02a0 2/11(total) h5 1 1 h10 db01 2 1 black jb03 470uf cb30 1 2 red jb01 10uf cb06 10uf cb20 10uf cb31 10uf cb01 10uf cb02 10uf cb11 10uf cb14 10uf cb05 gnd_tp06 gnd_tp01 gnd_tp03 gnd_tp05 h2 1 h4 1 .50standoff_nut h1 1 h3 1 gnd_tp02 gnd_tp04 0.1uf cb18 2 1 0.1uf cb16 2 1 0.1uf cb12 2 1 0.1uf cb10 2 1 0.1uf cb26 2 1 0.1uf cb21 2 1 0.1uf cb19 2 1 0.1uf cb23 2 1 0.1uf cb08 2 1 4.7uf cb04 4.7uf cb17 4.7uf cb13 0.1uf cb07 2 1 0.1uf cb41 2 1 4.7uf cb03 4.7uf cb38 0.1uf cb40 2 1 0.1uf c01 2 1 0.1uf cb32 2 1 4.7uf cb24 4.7uf cb25 4.7uf cb29 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 4 4 4 4 4 4 conn_banana_2p a b conn_banana_2p a b v3_3 v3_3 v3_3 v3_3 downloaded from: http:///
are in the micro processor block int_led and testpoints for addr/data/ctrl (low for parallel port) beginning of DS26521DK hierarchy block (high for moto mode) (high for normal operation) cr-3 : @\_ztop_lib\.\_ds26521topdn_\(sch_1):page1_i5@\_ztop_lib\.\_DS26521DK01a0dutdn_\(sch_1):page1 steve scully 1/3(block) 3/11(total) 10/26/2005 DS26521DK02a0 block name: _DS26521DK01a0dutdn_. parent block: \_ds26521topdn_\ 1b4^ 3c3 1b4^ 1b4^1b4^ 1c4^1c4^ 1b4^ ds01 rb12 ds02 rb13 rb36 rb39 rb35 rb40 2 3 1 jp07 rb38 2 3 1 jp10 rb45 rb46 rb37 2 3 1 jp09 2 3 1 jp08 2 3 1 jp05 2 3 1 jp06 10 9 8 7 6 5 4 3 2 1 j06 36 13 6 62 61 6059 64 7 6358 1 3 4 10 5554 52 57 11 5350 38 42 35 5649 39 47 4643 44 45 37 22 21 26 27 28 29 30 31 32 33 34 2 48 8 5 12 9 51 41 40 14 15 16 17 18 19 20 23 24 25 u03 rlf_ltc521 al_rsigf_flos521 i30 txenable521 bts521 spisel521 d5_spi_swapd6_spi_cpha d7_spi_cpol scanmo521 d_dut<7..0> 5 7 6 1.0k scanen521 7 1 1.0k 1.0k 1.0k 8 7 6 2 1 04 5 12 02 3 45 6 1.0k 3 a_dut<12..0> 1.0k 1.0k 1.0k d_dut<7..0> 330 i22 na rtip rchblk_clk521 bpclk521 bts521 spisel521 jtrst jtms jtclk jtdo scanen521 scanmo521 refclkio521 rd_dutwr_dut cs_x1 int521 mclk521 reset521 txenable521 al_rsigf_flos521 rsync521 rsysclk521rlf_ltc521 rm_rfsync521 rsig521 rser521rclk521 rring tsync521 tsig521 tchblk_clk521 tssyncio521 tsysclk521 tser521tclk521 tring ttip jtdi 330 3b4> 5c4<> 3c4> 5c4<> 3c8< 3d6< 3d6< 3a6< 3a4<> 1b4^ 3a6< 4b7< 5c4<> 5a3< 3b2< 3b2< 3a2< 3a2< 5b5<> 5d5< 3a2< 3a5<> 5c4<> 5b7<> 5a2<> 3a5<> 5c4<> 5b4<> 5b5< 5b7<5b3< 4b7< 5b5< 5b7<> 5b4<> 5b5< 5a2<> 5b5<>5b2<> 4b7< 4c7< page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 conn_10p 7 1 5 gnd 3 tck tms tdi vcc tdo v3_3 ds26521_u ttip tring tclk tser tsysclk tssynciotchblk/clk tsig a<0>a<1> a<2> a<4> a<7> a<6> a<5>a<8> a<12> tsync rring rclk rserrsig rm/rfsync rlf/ltc d<1>/spi_mosi d<2>/spi_clk d<5>/spi_swap d<4> rsysclk rsync al/rsigf/flos d<3> d<6>/spi_cpha txenable reset* mclk int* cs* wr/rw* rd/ds* atvdd refclkio acvdd dvdd dvss acvss arvss atvss scan_modescan_enable jtdo jtdi jtclk jtms jtrst spi_sel d<7>/spi_cpol bts d<0>/spi_miso bpclk rchblk/clk a<3> rtip arvdd v3_3 in in in in in io in downloaded from: http:///
cr-4 : @\_ztop_lib\.\_ds26521topdn_\(sch_1):page1_i5@\_ztop_lib\.\_DS26521DK01a0dutdn_\(sch_1):page2 block name: _DS26521DK01a0dutdn_. parent block: \_ds26521topdn_\ 2/3(block) 4/11(total) DS26521DK02a0 steve scully 10/26/2005 r01 r02 r03r04 cb09 2 1 cb15 2 1 rb30 2 1 rb31 2 1 rb41 1 2 3 4 1615 14 tb01 1 2 j08 5 6 7 8 11 10 9 tb01 8 7 6 5 4 3 2 1 jb02 1 2 j04 rtip 0.0 rring 0.0 0.0 tring ttip 560pf 61.9 61.9 51.1 .1uf 0.0 3c4<3c4< 3c7> 3c7> page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 1:1 1:0.8 conn_bnc_5pin 1:1 1:0.8 conn_rj48 e h f c b g d a conn_bnc_5pin downloaded from: http:///
end of DS26521DK hierarchy block cr-5 : @\_ztop_lib\.\_ds26521topdn_\(sch_1):page1_i5@\_ztop_lib\.\_DS26521DK01a0dutdn_\(sch_1):page3 10/26/2005 steve scully DS26521DK02a0 5/11(total) 3/3(block) block name: _DS26521DK01a0dutdn_. parent block: \_ds26521topdn_\ rb05 2 3 1 jp01 rb03 2 3 1 jp04 8 1 5 4 yb01 8 1 5 4 yb02 rb24 rb26 10 9 8 7 6 5 4 3 2 1 j02 rb23 rb11 rb25 10 9 8 7 6 5 4 3 2 1 j03 rb04 rb02 rb29 rb01 2 3 1 jp02 2 3 1 jp03 rb28 mclk521prebuf i56 rsysclk521 tsysclk521 jmp_3 bpclk521 rclk521 30 30 rsync521 30 refclkio521 jmp_3 1.544mhz_3.3v tsync521 tser521 tssyncio521 mclk521 mclk521prebuf 30 i58 2.048mhz_3.3v 30 rchblk_clk521 rm_rfsync521 tchblk_clk521 rlf_ltc521 al_rsigf_flos521 30 3030 30 jmp_3 bpclk521 mclk521prebuf mclk521prebuf jmp_3 30 30 tclk521 rsig521 mclk521prebuf tsig521 30 rser521 5d6<> 5a3< 5b3< 5b7< 3c4< 3c8< 3b4> 5a3< 3c4> 3c4<> 3d5<> 3c8<> 3c8< 3c8<> 3d6< 3b4>3c4> 3b8> 3a5<> 3b4> 3a5<> 3c4> 3b4> 5a3< 5d6<> 5a3< 5b3< 5b7< 5d6<> 5a3< 5b7< 3c8< 3c4> 5d6<> 5a3< 5b3< 3c8< 3c4> page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 vcc 1 osc gnd out v3_3 vcc 1 osc gnd out v3_3 6 10 8 4 1 2 3 5 7 9 conn_10p 6 10 8 4 1 2 3 5 7 9 conn_10p downloaded from: http:///
beginning of processor hierarchy block cr-6 : @\_ztop_lib\.\_ds26521topdn_\(sch_1):page1_i6@\_ztop_lib\.\_motprocrescard_dn\(sch_1):page1 printed wed oct 26 16:50:57 2005 DS26521DK02a0 1/6(block) 10/26/2005 steve scully 6/11(total) block name: _motprocrescard_dn. parent block: \_ds26521topdn_\ r05 c02 80 124 6669 142138 63 135 133 130 67 78 94 93 68 70 120 118 104105 106 107 108109 110 111 90 91 89 88 8482 7975 72 71 5253 54 55 56 57 58 61 125 9698 100 101 143 6062 81 8385 86 128 u04 92 126 73 114140 127 76 6444 32 18 8 112 113 87 123 103 74 115 141 129 77 6545 33 19 9 102 99 97 5995 3738 39 40 41 42 144 1 43 2 3 45 7 1012 15 16 17 46 20 21 2225 27 30 31 3435 36 48 51 1314 2324 26 28 29 116 117 119 47 121 122 131 132134 136 137 139 6 11 4950 u04 42 3 1 ub02 4 3 2 1 sw01 rb47cb22 pd<31..0> tim_16h_8l once_tms once_trst_b once_tclk osc_mcu spi_miso spi_mosi proc_reset spi_cs cs1 cs0 proc_reset_outonce_de_b eb0 spi_sck reset 1.0k proc_reset flash_vpp vddsyn 14 15 22 1 2 pa<22..0> gnd 14 15 16 11 12 13 16 18 17 1918 21 10 98 7 6 23 24 26 28 19 27 29 30 31 54 3 20 20 0.0 .1uf 0 1 4 21 3 5 6 7 98 10 11 12 13 22 2.93v 20 25 sci1_out sci2_in int3 user_led2 run_kit_usr int4 xtal yco cpuclk_out cs2 cse0 eb2 eb1 pqb1 eb3 cse1 2107_tdo once_tdi tc1 cs3 pqa1pqa0 pqa3 pqa4 icoc22 icoc23icoc20 icoc21icoc11 icoc12 icoc13 test icoc10 sci2_out user_led1 sci1_in rw tea vrh oe rcon ta tc2 17 1uf int2 kit_status pqb3pqb2 pqb0 7a2> 7a6> 7c7< 7d7< 9d6 8c1<> 8c2<> 8c3<> 8d5<> 8c3<> 6a4< 9d5<> 7b3<> 7b7<> 9d5<> 8c2<> 7b7<> 9d5<> 9c8<> 10c2> 11b4< 1b5^ 6b5<> 8c3<> 8b1<> 8b8< 10b6<> 10c3< 10c5< 10c3< 10c5< 8c5<> 9c8<> 9d5<> 7b4<> 9d4<> 8d3<> 8d3<> 8b8> 9d5<> 7b4<> 7b7<> 9d5<> 7d6< 8a3< page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 out out in out mmc2107control rxd1 int7* txd2 icoc10 test int1* icoc13icoc12 icoc11 icoc21 icoc20 icoc23icoc22 extal tclk trst* ss* pqb0pqa4 pqa3 pqa0 pqa1 cs3* tc1 tdi tdo cse1 eb3* int6* pqb1 pqb2 pqb3 eb0* eb1* eb2* tc2 cse0cs1* cs2* de* sck rstout* clkout reset* cs0* tms int0* yc0mosi misoxtal int3*int2* int5* int4 rxd2 txd1 mmc2107 port ta* shs* oe*vrh vstby tea*vddh vddf vdda vpp vdd6 vdd7 vdd8 vddsyn vdd3 vdd5 rw vrl a8 d31 a22 a21 a20a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9a7 a6 a5 a4 a3 a2 a1 a0 vss1 vss2 vss3 vss4 vss5 vss6 vss7 vss8 vsssyn vssf vssa d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d30d29 d28 d27 d26 d25 d24 d23 d22 d21d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 vdd2 vdd1 vdd4 v3_3 max811_u reset* vcc gnd mr* v3_3 downloaded from: http:///
xtal w/ pll boot internal d18 has a 10k load to gnd d18 has a 10.5k load to v3v boot ext when set for intern/extern boot reset configuration full drive master mode internal flash enable cr-7 : @\_ztop_lib\.\_ds26521topdn_\(sch_1):page1_i6@\_ztop_lib\.\_motprocrescard_dn\(sch_1):page2 block name: _motprocrescard_dn. parent block: \_ds26521topdn_\ 7/11(total) 2/6(block) 10/26/2005 steve scully DS26521DK02a0 2 1 rb19 2 1 1 rb09 2 1 rb21 2 1 1 rb08 2 1 1 rb15 2 1 rb20 1 2 1 rb18 1 2 1 rb16 2 1 1 rb14 29 32 24 1 21 20 1918 17 1514 13 16 30 22 2627 56 7 89 10 2 31 3 28 4 2523 11 12 u01 2 1 1 rb17 29 32 24 1 21 20 1918 17 1514 13 16 30 22 2627 56 7 89 10 2 31 3 28 4 2523 11 12 u02 18 pd<23..16> 23 rcon cs0 eb1oe cy62128v pa<17..1> cy62128v cs0 eb0 oe 17 15 1 2 3 4 5 6 7 8 1614 13 12 11 10 9 22 10k 31 30 2928 27 26 25 21 24 1 2 3 4 17 15 1614 13 19 5 6 7 8 12 11 10 9 20 10k 10k 17 10k10k 10k 10k 10k 10k 10k 16 pd<26>pd<17> pd<16> pd<21> pd<23> pd<22> pd<28> pd<19>pd<18> pd<31..24> pa<17..1> 6a2> 7c7< 7d7< 9d6 6d3<> 6b5<> 7b7<> 9d5<> 6d7<> 9d4<> 6d3<> 7b7<> 9d5<> 6a1> 7a8 9b8 6a2> 7a6> 9d6 6a2> 7a2> 9d6 6a2> 7a2> 9d6 6a2> 7a2> 9d6 6a2> 7a2> 9d6 6a2> 7a2> 9d6 6a2> 7a6> 9d6 6a2> 7a2> 9d6 6a2> 7c7< 7d7< 9d6 6a1> 7a5 9b8 page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 cy62128v ce1* ce2 a7a6 a5 a4 a3 a2 a1 a0 n_cwe* oe* gnd vcc a16a15 a14 a13 a12 a11 a10 a9a8 io0 io1 io2 io3 io4 io5 io6 io7 v3_3 cy62128v ce1* ce2 a7a6 a5 a4 a3 a2 a1 a0 n_cwe* oe* gnd vcc a16a15 a14 a13 a12 a11 a10 a9a8 io0 io1 io2 io3 io4 io5 io6 io7 v3_3 downloaded from: http:///
place pads for cap align key but do not populate cr-8 : @\_ztop_lib\.\_ds26521topdn_\(sch_1):page1_i6@\_ztop_lib\.\_motprocrescard_dn\(sch_1):page3 3/6(block) 10/26/2005 steve scully DS26521DK02a0 block name: _motprocrescard_dn. parent block: \_ds26521topdn_\ 8/11(total) 1 2 cb39 cb36 1 2 5 8 3 4 7 6 u06 1 2 1 rb52 2 1 ds04 1 2 j11 2 1 1 rb53 1 2 xb01 1 2 1 rb34 2 1 rb32 1 2 1 rb33 9 8 7 6 5 4 3 2 1 j05 1 2 1 rb10 1 2 1 rb22 9 1712 11 19 3 7 4 1 20 68 2 18 5 10 1615 14 13 ub01 2 1 rb27 2 1 1 rb43 14 13 12 11 10 9 8 7 6 5 4 3 2 1 j09 prt1_in 0.1uf kit_status flash_vpp green 10uf 1.0k prt1_out sci1_in sci1_out once_trst_b once_de_b once_tms con14p 10k osc_mcu prt1_in prt1_out xtal 10k 10k 10k 10k 10k 1.0m 8.0mhz proc_reset once_tclk 2107_tdo once_tdi 330 8a8<> 6a7<> 6d3< 8a8<> 6b8<> 6b8<> 6a6<> 6b5<> 6a6<> 6a6<> 8b8< 8b8> 6a7<> 6b5<> 6a4< 6a6<> 6d6<> 6d6<> page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 max1686_u cxp v3/5* pgnd gnd cxn out shdn in v3_3 v3_3 v3_3 conn_db9p h g f c a b de j v3_3 max3233e invalid* t2in t2out gnd v- c2-c2+ c1- c1+ v+2 v+1 forceoff* vcc t1out r1out forceon t1inr1in r2out r2in v3_3 con14p downloaded from: http:///
mem_sck must be at pin77 for tqfp144 cr-9 : @\_ztop_lib\.\_ds26521topdn_\(sch_1):page1_i6@\_ztop_lib\.\_motprocrescard_dn\(sch_1):page4 9/11(total) 4/6(block) DS26521DK02a0 steve scully 10/26/2005 block name: _motprocrescard_dn. parent block: \_ds26521topdn_\ rb51 ds05 rb50 111 112 113 114 115 116 118 119 120 121 122 123 124 127 129 130 131 132 133 134 135 137 138 139 140 141 142 100 101 102 103 104 105 106 107 74 75 76 77 78 79 81 82 83 85 8687 88 9 8 7 6 5 4 3 2 35 34 33 32 31 30 29 27 26 25 23 22 21 20 70 69 68 67 66 65 64 62 61 60 59 58 57 56 53 51 50 49 48 47 46 45 43 42 41 40 39 u05 8 a_dut_<12..0> 6 12 9 cs_x5 cs_x4 cs_x3 mem_si mem_cs eb1 eb0 mem_sck 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 2 1 0 cpuclk_out 27 29 31 30 2826 25 24 22 21 20 1918 17 16 pa<16..0> d_dut<7..0> 7 65 4 3 2 1 0 rd_dut int2 oerw cs0 cs1 cs2 reset cs_x2 cs_x1 23 pd<31..16> wr_dut ale_dut int_led 330 int5 0.0 userfpga2 mem_so 97_io 3 4 7 tristate_ad_bus 10b2> 10b7 1b5^ 10b2> 10a6<> 10b2> 10a6<> 10b2> 11c8<11b8< 6d7<> 7b4<> 6d7<> 7b7<> 6b5<> 10b2<> 10a6 1b5^ 10a6<> 10b2> 1b5^ 6a7<> 10b6<> 10c3< 10c5< 1c5^ 6d4<>6b5<> 6c5<> 6a4<> 10c2> 11b4< 1b5^ 10a6<> 10b2> 10a6<> 10b2> 1c5^ 6a2> 7a2> 7a6> 7c7< 7d7< 10a6<> 10b2> 1b5^ 10c3< 10c5< 11c8> 10b6<> page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 bank 3 lfec_t144_u bank 0 i/o port bank 6 bank 4 bank 5 bank 1 bank 2 input pll pll input pll input bank 7 input pll input pll pll input pl9b/pclkc7_0 pt16b/vref1_0 pt17a/pclkt0_0 pt15apt15b pt16a/vref2_0 pr14a/rlm0_pllt_fb_a pr12a/dout/cso* pt14b pl14a pl13b pl13a pt12b pt12a pb17a/pclkt5_0pb19a/vref1_4 pb19b/cs* pb20a/vref2_4 pt14a/tdqs14 pt10apt10b pb10bpb23a pb22a/bdqs22 pb21a/d2/spid5 pb18b/cs1* pl11a/llm0_pllt_in_apl11b/llm0_pllc_in_a pl12a/llm0_pllt_fb_a pl12b/llm0_pllc_fb_a pl14b pl15b pl15a/ldqs15pl16b pl18b/vref2_6 pl18a/vref1_6 pb18a/write* pb17b/pclkc5_0 pb16a/vref2_5pb16b/vref1_5 pb15b pb15a pb14b pb14a/bdqs14 pb13b pb11b pb11a pb10a pl16a pb20b/d0/spid7pb21b/d1/spid6 pb22b/d3/spid4 pb23b/d4/spid3 pb25b/d6/spid1 pb24b/d5/spid2 pl2a/vref2_7pl2b/vref1_7 pl7a pl7bpl8b pl8a pt25b pt25a pt23a pt22b pt22a/tdqs22 pt21b pt20apt21a pt20b pt19b/vref2_1 pt13b pt13a pt19a/vref1_1 pt18b pt18a pr2b/vref1_2 pr2a/vref2_2 pr7b pr7apr8a pr8b pr9a/pclkt2_0pr9b/pclkc2_0 pr13a/rlm0_pllt_in_apr13b/rlm0_pllc_in_a pr14b/rlm0_pllc_fb_a pr15a/rdqs15 pr16a pr18a/vref1_3 pr16b pl9a/pclkt7_0 pr15b pt17b/pclkc0_0 pr11a/d7/spid0 pr11b/busy/sispi pr12b/di/csspi* downloaded from: http:///
jumper pins 12+14 to tristate the address databuss of the fpga. this allows the user to connect a different processor cr-10 : @\_ztop_lib\.\_ds26521topdn_\(sch_1):page1_i6@\_ztop_lib\.\_motprocrescard_dn\(sch_1):page5 10/11(total) 10/26/2005 steve scully DS26521DK02a0 5/6(block) block name: _motprocrescard_dn. parent block: \_ds26521topdn_\ 9a6 10a6 1b5^ 6a7<> 10b6<> 10c5< 6a7<> 9c4<> 10b6<> 10c5< 1c5^ 9c4<> 10a6<> 1b5^ 9c4<> 10a6<> 1b5^ 9b4<> 10c5< 6a7<> 10c5< 6a4<> 9c8<> 11b4< 1b5^ 9a4<> 10a6<> 9a7<> 10a6<> 9a7<> 10a6<> 1c5^ 9a5<> 9a5<> 10a6<> 9a6 10b7 1b5^ 2 1 r07 14 13 12 11 10 9 8 7 6 5 4 3 2 1 j10 14 13 12 11 10 9 8 7 6 5 4 3 2 1 j07 2 1 rb54 2 1 rb44 2 1 r06 2 1 rb55 tristate_ad_bus int3 10k d_dut<7..0> cs_x4 a_dut_<12..0> 12 3 d_dut<7..0> 2 1 0 int5 nopop 0 int3int2 wr_dutrd_dut int5int4 reset 10k 10k int4 1 2 3 45 6 7 nopop int2 10k cs_x3 cs_x2 cs_x1 cs_x5 cs_x4 a_dut_<12..0> 4 5 6 7 8 10k int2 int3 wr_dut rd_dut cs_x1 cs_x2 cs_x3 9c3> 6a7<> 10b6<> 10c3< 9a5<> 10b2> 9b4<> 10c3< 6a7<> 10c3< 6a7<> 9c4<> 10b6<> 10c3< 1c5^ 6a7<> 9c4<> 10c3< 10c5< 1c5^ 6a7<> 10c3< 10c5< 9c4<> 10b2> 1b5^ 9c4<> 10b2> 1b5^ 9a7<> 10b2> 1c5^ 9a7<> 10b2> 9a4<> 10b2> page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 out out out v3_3 out out 2 3 7 13 8 59 11 6 4 1012 14 1 conn_14p 2 3 7 13 8 59 11 6 4 1012 14 1 conn_14p out out in in inin io out out v3_3 downloaded from: http:///
end of processor hierarchy block cr-11 : @\_ztop_lib\.\_ds26521topdn_\(sch_1):page1_i6@\_ztop_lib\.\_motprocrescard_dn\(sch_1):page6 11/11(total) 6/6(block) 10/26/2005 steve scully DS26521DK02a0 block name: _motprocrescard_dn. parent block: \_ds26521topdn_\ 3 4 6 1 5 2 ub05 3 8 2 56 7 4 1 ub04 10 9 8 7 6 5 4 3 2 1 j01 cb27cb33 cb35 cb37 cb34 cb28 rb07rb06 10 19 1 36 24 44 38 71 55 84 73 108 125 110 143 136 126 54 99 92 13 17 18 16 14 93 12 11 95 96 15 144 37 28 52 63 80 72 109 98 117 128 97 8990 91 94 u05 rb48 1 tp01 1 tp02 rb42 i6 mem_sck 10k i5 i28 i26 i24 i10 mem_si mem_somem_sck mem_cs l_tdo l_tdi l_tdi l_tdo reset l_tms l_tck v1_2 l_tck l_tms v1_2 2.7v .1uf.1uf .1uf 10uf 10uf 10uf 10k10k 97_io 10k 9b3< 11b8< 9c4<> 9c4<> 11b1<> 9b3< 9b4<> 11c4> 11c4< 11d6<>11d6<> 6a4<> 9c8<> 10c2> 1b5^ 11d6<> 11d6<> 11c1< 11c4< 11c4< 11a6< page: date: title: engineer: a a b b c c d d 1 1 2 2 3 3 4 4 5 5 6 6 7 7 88 v3_3 max1963 shdn* gnd rst* out ic in v3_3 at25160a_u si gnd wp* hold* vcc so sckcs* conn_10p 7 1 5 gnd 3 tck tms tdi vcc tdo v3_3 v3_3 control lfec_t144_u all low for spi3 mode needs 10k,1% resistor place close to pin vccio4a vccio3b xres vccaux2 vccaux1 vccj vcc3 tdi tdo vccio3avccio4b vccio5a vccio2 vccio1b vccio1a vccio0b init* program* vccio0a cclk cfg1 cfg2cfg0 tms vcc2 vcc1 vccio5bvccio6a tck done gnd10 gnd9 gnd8 gnd7/gnd0 gnd6b/gnd5 gnd3b gnd3a/gnd4 gnd2/gnd1 gnd1 gnd0 nc1 nc2 gnd4 gnd6a gnd5 vccio7 vccio6b v3_3 downloaded from: http:///

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